View MAX12557_947368.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-3544; Rev 0; 2/05
KIT ATION EVALU ABLE AVAIL
Dual, 65Msps, 14-Bit, IF/Baseband ADC
General Description
The MAX12557 is a dual 3.3V, 14-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving internal quantizers. The MAX12557 is optimized for low power, small size, and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual ADC operates from a single 3.3V supply, consuming only 610mW while delivering a typical 72.5dB signal-tonoise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or differential inputs up to 400MHz. In addition to low operating power, the MAX12557 features a 166W powerdown mode to conserve power during idle periods. A flexible reference structure allows the MAX12557 to use the internal 2.048V bandgap reference or accept an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range to be adjusted from 0.35V to 1.15V. The MAX12557 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12557 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2) and divide-by-four (DIV4) modes allow for design flexibility and help eliminate the negative effects of clock jitter. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer (DCE). The MAX12557 features two parallel, 14-bit-wide, CMOS-compatible outputs. The digital output format is pin-selectable to be either two's complement or Gray code. A separate power-supply input for the digital outputs accepts a 1.7V to 3.6V voltage for flexible interfacing with various logic levels. The MAX12557 is available in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package with exposed paddle (EP), and is specified for the extended (-40C to +85C) temperature range. For a 12-bit, pin-compatible version of this ADC, refer to the MAX12527 data sheet.
Features
Direct IF Sampling Up to 400MHz Excellent Dynamic Performance 74.1dB/72.5dB SNR at fIN = 70MHz/175MHz 83.4dBc/79.5dBc SFDR at fIN = 70MHz/175MHz 3.3V Low-Power Operation 637mW (Differential Clock Mode) 610mW (Single-Ended Clock Mode) Fully Differential or Single-Ended Analog Input Adjustable Differential Analog Input Voltage 750MHz Input Bandwidth Adjustable, Internal or External, Shared Reference Differential or Single-Ended Clock Accepts 25% to 75% Clock Duty Cycle User-Selectable DIV2 and DIV4 Clock Modes Power-Down Mode CMOS Outputs in Two's Complement or Gray Code Out-of-Range and Data-Valid Indicators Small, 68-Pin Thin QFN Package 12-Bit Compatible Version Available (MAX12527) Evaluation Kit Available (Order MAX12557 EV Kit)
MAX12557
Ordering Information
PART MAX12557ETK TEMP RANGE -40C to +85C PIN-PACKAGE 68 Thin QFN-EP* (10mm x 10mm x 0.8mm)
*EP = Exposed paddle.
Selector Guide
PART MAX12557 MAX12527 SAMPLING RATE (Msps) 65 65 RESOLUTION (Bits) 14 12
Applications
IF and Baseband Communication Receivers Cellular, LMDS, Point-to-Point Microwave, MMDS, HFC, WLAN I/Q Receivers Ultrasound and Medical Imaging Portable Instrumentation Digital Set-Top Boxes Low-Power Data Acquisition
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
ABSOLUTE MAXIMUM RATINGS
VDD to GND ................................................................-0.3V to +3.6V OVDD to GND............-0.3V to the lower of (VDD + 0.3V) and +3.6V INAP, INAN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V INBP, INBN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN to GND ........................-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT to GND ..................-0.3V to the lower of (VDD + 0.3V) and +3.6V REFAP, REFAN, COMA to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V REFBP, REFBN, COMB to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V DIFFCLK/SECLK, G/T, PD, SHREF, DIV2, DIV4 to GND .........-0.3V to the lower of (VDD + 0.3V) and +3.6V D0A-D13A, D0B-D13B, DAV, DORA, DORB to GND..............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 68-Pin Thin QFN 10mm x 10mm x 0.8mm (derate 70mW/C above +70C) ....................................4000mW Operating Temperature Range................................-40C to +85C Junction Temperature ...........................................................+150C Storage Temperature Range .................................-65C to +150C Lead Temperature (soldering 10s).......................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, VIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 65MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT (INAP, INAN, INBP, INBN) Differential Input Voltage Range Common-Mode Input Voltage Analog Input Resistance RIN CPAR Analog Input Capacitance CSAMPLE CONVERSION RATE Maximum Clock Frequency Minimum Clock Frequency Data Latency Figure 5 8 fCLK 65 5 MHz MHz Clock Cycles dBFS Switched capacitance, each input, Figure 3 4.5 Each input, Figure 3 Fixed capacitance to ground, each input, Figure 3 VDIFF Differential or single-ended inputs 1.024 VDD / 2 3.4 2 pF V V k INL DNL fIN = 3MHz fIN = 3MHz, no missing codes over temperature (Note 2) -1.0 14 2.1 0.6 0.1 0.5 +1.3 0.9 5.0 Bits LSB LSB %FSR %FSR SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS (differential inputs) Small-Signal Noise Floor SSNF Input at -35dBFS fIN = 3MHz at -0.5dBFS Signal-to-Noise Ratio SNR fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS 70.4 74.5 72.5 76 75 74.5 74.1 72.5 dB
2
_______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, VIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 65MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS fIN = 3MHz at -0.5dBFS (Note 3) Signal-to-Noise Plus Distortion SINAD fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS (Note 3) Spurious-Free Dynamic Range SFDR fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS (Note 3) Total Harmonic Distortion THD fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Second Harmonic HD2 fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Third Harmonic HD3 fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS Two-Tone Intermodulation Distortion (Note 2) fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS Input at -0.2dBFS, -3dB rolloff Figure 5 INAP = INAN = COMA INBP = INBN = COMB 75.5 MIN 71.8 TYP 74.4 73.10 73.4 71.5 86.6 82.8 83.4 79.5 -84.5 -80.7 -81.7 -78.3 -89.5 -84.2 -84.7 -79.5 -93 -85.5 -86.5 -87.2 -88 dBc -82.4 -91.5 dBc -87.6 89 dBc 82.4 750 1.2 <0.15 1.02 MHz ns psRMS LSBRMS dBc dBc -74.5 dBc dBc dB MAX UNITS
MAX12557
TTIMD
3rd-Order Intermodulation Distortion
IM3
Two-Tone Spurious-Free Dynamic Range Full-Power Bandwidth Aperture Delay Aperture Jitter Output Noise
SFDRTT
FPBW tAD tAJ nOUT
_______________________________________________________________________________________
3
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, VIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 65MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Overdrive Recovery Time INTERCHANNEL CHARACTERISTICS Crosstalk Rejection Gain Matching Offset Matching INTERNAL REFERENCE (REFOUT) REFOUT Output Voltage REFOUT Load Regulation REFOUT Temperature Coefficient REFOUT Short-Circuit Current TCREF Short to VDD--sinking Short to GND--sourcing VREFOUT -1mA < IREFOUT < +1mA 2.000 2.048 35 50 0.24 2.1 2.080 V mV/mA ppm/C mA fINA or fINB = 70MHz at -0.5dBFS fINA or fINB = 175MHz at -0.5dBFS 90 85 0.01 0.01 0.1 dB dB %FSR SYMBOL CONDITIONS 10% beyond full scale MIN TYP 1 MAX UNITS Clock Cycle
BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source; VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are generated internally) REFIN Input Voltage REFIN Input Resistance COM_ Output Voltage REF_P Output Voltage REF_N Output Voltage Differential Reference Voltage Differential Reference Temperature Coefficient VREFIN RREFIN VCOMA VCOMB VREFAP VREFBP VREFAN VREFBN VREFA VREFB TCREF VDD / 2 VDD / 2 + (VREFIN x 3/8) VDD / 2 - (VREFIN x 3/8) VREFA = VREFAP - VREFAN VREFB = VREFBP - VREFBN 1.460 1.60 2.048 >50 1.65 2.418 0.882 1.536 25 1.580 1.70 V M V V V V ppm/C
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are applied externally, VCOMA = VCOMB = VDD / 2) REF_P Input Voltage REF_N Input Voltage COM_ Input Voltage Differential Reference Voltage VREFAP VREFBP VREFAN VREFBN VCOM VREFA VREFB VREF_P - VCOM VREF_N - VCOM VDD / 2 VREF_ = VREF_P - VREF_N = VREFIN x 3/4 +0.768 -0.768 1.65 1.536 V V V V
4
_______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, VIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 65MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER REF_P Sink Current REF_N Source Current COM_ Sink Current REF_P, REF_N Capacitance COM_ Capacitance CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold Single-Ended Input Low Threshold Minimum Differential Clock Input Voltage Swing Differential Input Common-Mode Voltage CLK_ Input Resistance CLK_ Input Capacitance RCLK CCLK 0.8 x OVDD 0.2 x OVDD 5 5 5 D0A-D13A, D0B-D13B, DORA, DORB: ISINK = 200A DAV: ISINK = 600A D0A-D13A, D0B-D13B, DORA, DORB: ISOURCE = 200A DAV: ISOURCE = 600A Tri-State Leakage Current (Note 3) ILEAK OVDD applied to input Input connected to ground OVDD 0.2 V OVDD 0.2 5 5 A VIH VIL DIFFCLK/SECLK = GND, CLKN = GND DIFFCLK/SECLK = GND, CLKN = GND DIFFCLK/SECLK = OVDD DIFFCLK/SECLK = OVDD Each input, Figure 4 0.2 VDD / 2 5 2 0.8 x VDD 0.2 x VDD V V VP-P V k pF SYMBOL IREFAP IREFBP IREFAN IREFBN ICOMA ICOMB CREF_P, CREF_N CCOM_ CONDITIONS VREF_P = 2.418V VREF_N = 0.882V VCOM_ = 1.65V MIN TYP 1.2 0.85 0.85 13 6 MAX UNITS mA mA mA pF pF
MAX12557
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4) Input High Threshold Input Low Threshold Input Leakage Current Digital Input Capacitance CDIN VIH VIL OVDD applied to input Input connected to ground V V A pF
DIGITAL OUTPUTS (D0A-D13A, D0B-D13B, DORA, DORB, DAV) Output-Voltage Low VOL 0.2 0.2 V
Output-Voltage High
VOH
_______________________________________________________________________________________
5
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, VIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 65MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER D0A-D13A, DORA, D0B-D13B and DORB Tri-State Output Capacitance (Note 3) DAV Tri-State Output Capacitance (Note 3) POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage VDD OVDD Normal operating mode fIN = 175MHz at -0.5dBFS, single-ended clock (DIFFCLK/SECLK = GND) Analog Supply Current IVDD Normal operating mode fIN = 175MHz at -0.5dBFS differential clock (DIFFCLK/SECLK = OVDD) Power-down mode (PD = OVDD) clock idle Normal operating mode fIN = 175MHz at -0.5dBFS single-ended clock (DIFFCLK/SECLK = GND) Analog Power Dissipation PVDD Normal operating mode fIN = 175MHz at -0.5dBFS differential clock (DIFFCLK/SECLK = OVDD) Power-down mode (PD = OVDD) clock idle Normal operating mode fIN = 175MHz at -0.5dBFS Power-down mode (PD = OVDD) clock idle 3.15 1.70 3.30 2.0 3.60 VDD V V SYMBOL COUT CONDITIONS MIN TYP 3 MAX UNITS pF
CDAV
6
pF
185
mA 193 210
0.05
610
mW 637 693
0.165 21.3 mA 0.001
Digital Output Supply Current
IOVDD
6
_______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, VIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 65MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Clock Pulse-Width High Clock Pulse-Width Low Data-Valid Delay Data Setup Time Before Rising Edge of DAV Data Hold Time After Rising Edge of DAV Wake-Up Time from Power-Down SYMBOL tCH tCL tDAV tSETUP tHOLD tWAKE (Note 6) (Note 6) VREFIN = 2.048V 7.0 7.0 10 CONDITIONS MIN TYP 7.7 7.7 5.4 MAX UNITS ns ns ns ns ns ms
MAX12557
TIMING CHARACTERISTICS (Figure 5)
Specifications +25C guaranteed by production test, <+25C guaranteed by design and characterization. Guaranteed by design and characterization. Device tested for performance during product test. Specification guaranteed by production test for +25C. Two-tone intermodulation distortion measured with respect to a single-carrier amplitude, and not the peak-to-average input power of both input tones. Note 5: During power-down, D0A-D13A, D0B-D13B, DORA, DORB, and DAV are high impedance. Note 6: Guaranteed by design and characterization. Note 1: Note 2: Note 3: Note 4:
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
FFT PLOT (32,768-POINT DATA RECORD)
MAX12557 toc01
FFT PLOT (32,768-POINT DATA RECORD)
MAX12557 toc02
FFT PLOT (32,768-POINT DATA RECORD)
-10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 fCLK = 65.00352MHz fIN = 70.00852MHz AIN = -0.498dBFS SNR = 74.41dB SINAD = 74.00dB THD = -84.50dBc SFDR = 86.25dBc HD2 HD3
MAX12557 toc03
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 HD2
AMPLITUDE (dBFS)
fCLK = 65MHz fIN = 3.00125MHz AIN = -0.48dBFS SNR = 74.45dB SINAD = 74.33dB THD = -90.06dBc SFDR = 92.47dBc HD3
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 HD2
fCLK = 65.00352MHz fIN = 32.40058MHz AIN = -0.424dBFS SNR = 74.77dB SINAD = 74.62dB THD = -87.22dBc SFDR = 91.88dBc HD3
0
20
25
30
0
5
10
15
20
25
30
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
7
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
FFT PLOT (32,768-POINT DATA RECORD)
MAX12557 toc04
TWO-TONE IMD PLOT (16,384-POINT DATA RECORD)
MAX12557 toc05
TWO-TONE IMD PLOT (16,384-POINT DATA RECORD)
-10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 fCLK = 65.00352MHz fIN1 = 172.49995MHz AIN1 = -6.95dBFS fIN2 = 177.49900688MHz AIN2 = -6.97dBFS IM3 = -87.61dBc IMD = -82.37dBc
MAX12557 toc06
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 fIN1
fCLK = 65.00352MHz fIN = 174.98857MHz AIN = -0.476dBFS SNR = 72.37dB SINAD = 70.48dB THD = -75.62dBc SFDR = 76.37dBc HD3 HD2
fIN2
fCLK = 65.00352MHz fIN1 = 68.49987MHz AIN1 = -6.97dBFS fIN2 = 71.49930dB AIN2 = -6.99dBFS IM3 = -91.54dBc IMD = -87.97dBc 2fIN2 + fIN1 HD3
0
fIN1
fIN2 fIN1 + fIN2
2fIN1 + fIN2
HD3
HD2
30 5 10 15 20 25 ANALOG INPUT FREQUENCY (MHz)
0
5 10 15 20 25 30 ANALOG INPUT FREQUENCY (MHz)
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (4,194,304-POINT DATA RECORD)
MAX12557 toc07
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE (4,194,304-POINT DATA RECORD)
MAX12557 toc08
1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0
fIN = 3.00123MHz
0.75 0.50 DNL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00
fIN = 3.00123MHz
75 70 SNR, SINAD (dB) 65 60 55 50 45 40 SINAD
SNR
2048 4096 6144 8192 10240 12288 14336 16384 DIGITAL OUTPUT CODE
0
2048 4096 6144 8192 10240 12288 14336 16384 DIGITAL OUTPUT CODE
0
50
100 150 200 250 300 350 400 fIN (MHz)
-THD, SFDR vs. ANALOG INPUT FREQUENCY (fCLK = 65.00352MHz, AIN = -0.5dBFS)
MAX12557 toc10
SNR, SINAD vs. ANALOG INPUT AMPLITUDE (fCLK = 65.00352MHz, fIN = 70MHz)
MAX12557 toc11
-THD, SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 65.00352MHz, fIN = 70MHz)
SFDR
MAX12557 toc12
95 90 85 -THD, SFDR (dBc) SFDR 80 75 70 65 60 55 50 0 50 -THD
80 SNR 70 SNR, SINAD (dB) 60 50 SINAD 40 30 20
95 85 -THD, SFDR (dBc) 75 65 -THD 55 45 35
100 150 200 250 300 350 400 fIN (MHz)
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 AIN (dBFS)
0
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 AIN (dBFS)
0
8
_______________________________________________________________________________________
MAX12557 toc09
2.0
1.00
SNR, SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 65.00352MHz, AIN = -0.5dBFS)
80
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
SNR, SINAD vs. ANALOG INPUT AMPLITUDE (fCLK = 65.00352MHz, fIN = 175MHz)
SNR 70 SNR, SINAD (dB) 60 50 40 30 20 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 AIN (dBFS) 0 SINAD
MAX12557 toc13
-THD, SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 65.00352MHz, fIN = 175MHz)
MAX12557 toc14
SNR, SINAD vs. CLOCK SPEED (fIN = 70MHz, AIN = -0.5dBFS)
MAX12557 toc15
80
95 85 -THD, SFDR (dBc) 75 65 55 45 35 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 AIN (dBFS) 0 -THD SFDR
80
76 SNR, SINAD (dB)
SNR
72
SINAD
68
64
60 20 25 30 35 40 45 50 55 60 65 fCLK (MHz)
-THD, SFDR vs. CLOCK SPEED (fIN = 70MHz, AIN = -0.5dBFS)
MAX12557 toc16
SNR, SINAD vs. CLOCK SPEED (fIN = 175MHz, AIN = -0.5dBFS)
MAX12557 toc17
-THD, SFDR vs. CLOCK SPEED (fIN = 175MHz, AIN = -0.5dBFS)
MAX12557 toc18
90 SFDR 85 -THD, SFDR (dBc) 80 75 70 65 60 20 25 30 35 40 45 50 55 60 -THD
80
90 85 -THD, SFDR (dBc) 80 75 70 65 60 -THD SFDR
76 SNR, SINAD (dB)
SNR
72 SINAD
68
64
60 65 20 25 30 35 40 45 50 55 60 65 fCLK (MHz) fCLK (MHz)
20
25
30
35
40
45
50
55
60
65
fCLK (MHz)
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 70MHz)
MAX12557 toc19
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 70MHz)
MAX12557 toc20
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 175MHz)
SNR 72 SNR, SINAD (dB)
MAX12557 toc21
80 SNR 76 SNR, SINAD (dB)
95 90 -THD, SFDR (dBc) 85 80 75 70 -THD SFDR
75
72
SINAD
69
SINAD
68
66
64 65 60 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 60 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6
63
60 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6
_______________________________________________________________________________________
9
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 175MHz)
MAX12557 toc22
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 70MHz)
MAX12557 toc23
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 70MHz)
SFDR
MAX12557 toc24
85
80 SNR 76 SNR, SINAD (dB)
95 90 -THD, SFDR (dBc) 85 80 75 70 -THD
80 -THD, SFDR (dBc)
SFDR
75 -THD 70
72 SINAD 68
65
64 65
60 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6
60 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 OVDD (V)
60 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 OVDD (V)
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 175MHz)
MAX12557 toc25
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 175MHz)
MAX12557 toc26
PDISS, IVDD (ANALOG) vs. ANALOG SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 175MHz)
800 700 PDISS, IVDD (mW, mA) 600 500 400 300 200 100 IVDD
MAX12557 toc27
75 SNR 72 SNR, SINAD (dB)
80 SFDR 76 -THD, SFDR (dBc)
900 PDISS (ANALOG)
69 SINAD 66
72 -THD 68
63
64
60 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 OVDD (V)
60 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 OVDD (V)
0 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6
PDISS, IOVDD (DIGITAL) vs. DIGITAL SUPPLY VOLTAGE (fCLK = 65.00352MHz, fIN = 175MHz)
MAX12557 toc28
SNR, SINAD vs. CLOCK DUTY CYCLE (fIN = 70MHz, AIN = -0.5dBFS)
MAX12557 toc29
-THD, SFDR vs. CLOCK DUTY CYCLE (fIN = 70MHz, AIN = -0.5dBFS)
SFDR
MAX12557 toc30
80 70 PDISS, IOVDD (mW, mA) 60 CL 5pF
72 SNR 70 SNR, SINAD (dB) 68 66 64 62 SINGLE-ENDED CLOCK DRIVE 60
90 85 -THD, SFDR (dBc) 80 -THD 75 70 65
50 40 30 20 10 0 1.5 1.8
PDISS (DIGITAL)
SINAD
IOVDD
SINGLE-ENDED CLOCK DRIVE 60 75 25 35 45 55 65 75
2.1
2.4
2.7
3.0
3.3
3.6
25
35
45
55
65
OVDD (V)
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
10
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
SNR, SINAD vs. TEMPERATURE (fIN = 175MHz, AIN = -0.5dBFS)
MAX12557 toc31
-THD, SFDR vs. TEMPERATURE (fIN = 175MHz, AIN = -0.5dBFS)
MAX12557 toc32
76 74 72 SNR
90 85 SFDR -THD, SFDR (dBc) 80 75 70 65 60 -THD
SNR, SINAD (dB)
70 68 66 64 62 60 -40 -15 10 35 60 85 TEMPERATURE (C) SINAD
-40
-15
10
35
60
85
TEMPERATURE (C)
GAIN ERROR vs. TEMPERATURE
MAX12557 toc33
OFFSET ERROR vs. TEMPERATURE
MAX12557 toc34
3 2 GAIN ERROR (%FSR) 1 0 -1 -2 -3 -40 -15 10 35 60
0.3 0.2 OFFSET ERROR (%FSR) 0.1 0 -0.1 -0.2 -0.3
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
______________________________________________________________________________________
11
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Pin Description
PIN 1, 4, 5, 9, 13, 14, 17 2 3 6 NAME GND INAP INAN COMA FUNCTION Converter Ground. Connect all ground pins and the exposed paddle (EP) together. Channel A Positive Analog Input Channel A Negative Analog Input Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1F capacitor. Channel A Positive Reference I/O. Channel A conversion range is 2/3 x (VREFAP - VREFAN). Bypass REFAP with a 0.1F capacitor to GND. Connect a 10F and a 1F bypass capacitor between REFAP and REFAN. Place the 1F REFAP-to-REFAN capacitor as close to the device as possible on the same side of the PC board. Channel A Negative Reference I/O. Channel A conversion range is 2/3 x (VREFAP - VREFAN). Bypass REFAN with a 0.1F capacitor to GND. Connect a 10F and a 1F bypass capacitor between REFAP and REFAN. Place the 1F REFAP-to-REFAN capacitor as close to the device as possible on the same side of the PC board. Channel B Negative Reference I/O. Channel B conversion range is 2/3 x (VREFBP - VREFBN). Bypass REFBN with a 0.1F capacitor to GND. Connect a 10F and a 1F bypass capacitor between REFBP and REFBN. Place the 1F REFBP-to-REFBN capacitor as close to the device as possible on the same side of the PC board. Channel B Positive Reference I/O. Channel B conversion range is 2/3 x (VREFBP - VREFBN). Bypass REFBP with a 0.1F capacitor to GND. Connect a 10F and a 1F bypass capacitor between REFBP and REFBN. Place the 1F REFBP-to-REFBN capacitor as close to the device as possible on the same side of the PC board. Channel A Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1F capacitor. Channel B Negative Analog Input Channel B Positive Analog Input Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock input drives. DIFFCLK/SECLK = GND: Selects single-ended clock input drive. DIFFCLK/SECLK = OVDD: Selects differential clock input drive. Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the clock signal to CLKP and connect CLKN to GND. Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the single-ended clock signal to CLKP and connect CLKN to GND. Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details. Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details. Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel capacitor combination of 10F and 0.1F. Connect all VDD pins to the same potential. Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of 10F and 0.1F.
7
REFAP
8
REFAN
10
REFBN
11
REFBP
12 15 16
COMB INBN INBP DIFFCLK/ SECLK
18
19
CLKN
20 21 22 23-26, 61, 62, 63 27, 43, 60
CLKP DIV2 DIV4 VDD OVDD
12
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Pin Description (continued)
PIN 28 29 30 31 32 33 34 35 36 37 38 39 40 41 NAME D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B D10B D11B D12B D13B Channel B CMOS Digital Output, Bit 0 (LSB) Channel B CMOS Digital Output, Bit 1 Channel B CMOS Digital Output, Bit 2 Channel B CMOS Digital Output, Bit 3 Channel B CMOS Digital Output, Bit 4 Channel B CMOS Digital Output, Bit 5 Channel B CMOS Digital Output, Bit 6 Channel B CMOS Digital Output, Bit 7 Channel B CMOS Digital Output, Bit 8 Channel B CMOS Digital Output, Bit 9 Channel B CMOS Digital Output, Bit 10 Channel B CMOS Digital Output, Bit 11 Channel B CMOS Digital Output, Bit 12 Channel B CMOS Digital Output, Bit 13 (MSB) Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog input voltage is out of range. DORB = 1: Digital outputs exceed full-scale range. DORB = 0: Digital outputs are within full-scale range. Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs. The MAX12557 evaluation kit utilizes DAV to latch data into any external back-end digital logic. Channel A CMOS Digital Output, Bit 0 (LSB) Channel A CMOS Digital Output, Bit 1 Channel A CMOS Digital Output, Bit 2 Channel A CMOS Digital Output, Bit 3 Channel A CMOS Digital Output, Bit 4 Channel A CMOS Digital Output, Bit 5 Channel A CMOS Digital Output, Bit 6 Channel A CMOS Digital Output, Bit 7 Channel A CMOS Digital Output, Bit 8 Channel A CMOS Digital Output, Bit 9 Channel A CMOS Digital Output, Bit 10 Channel A CMOS Digital Output, Bit 11 Channel A CMOS Digital Output, Bit 12 Channel A CMOS Digital Output, Bit 13 (MSB) Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog input voltage is out of range. DORA = 1: Digital outputs exceed full-scale range. DORA = 0: Digital outputs are within full-scale range. Output Format Select Digital Input. G/T = GND: Two's-complement output format selected. G/T = OVDD: Gray-code output format selected. FUNCTION
42
DORB
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
DAV D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A DORA
64
G/T
______________________________________________________________________________________
13
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Pin Description (continued)
PIN 65 NAME PD Power-Down Digital Input. PD = GND: ADCs are fully operational. PD = OVDD: ADCs are powered down. Shared Reference Digital Input. SHREF = VDD: Shared reference enabled. SHREF = GND: Shared reference disabled. When sharing the reference, externally connect REFAP and REFBP together to ensure that VREFAP = VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure that VREFAN = VREFBN. Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a 0.1F capacitor. For external reference operation, REFOUT is not required and must be bypassed to GND with a 0.1F capacitor. Single-Ended Reference Analog Input. For internal reference and buffered external reference operation, apply a 0.7V to 2.3V DC reference voltage to REFIN. Bypass REFIN to GND with a 4.7F capacitor. Within its specified operating voltage, REFIN has a >50M input impedance, and the differential reference voltage (VREF_P - VREF_N) is generated from REFIN. For unbuffered external reference operation, connect REFIN to GND. In this mode, REF_P, REF_N, and COM_ are high-impedance inputs that accept the external reference voltages. Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified dynamic performance. FUNCTION
66
SHREF
67
REFOUT
68
REFIN
--
EP
+ MAX12557
FLASH ADC DAC
-
x2
IN_P STAGE 1 IN_N DIGITAL ERROR CORRECTION STAGE 2 STAGE 9
STAGE 10 END OF PIPELINE
D0_ THROUGH D13_
Figure 1. Pipeline Architecture--Stage Blocks
Detailed Description
The MAX12557 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output the total latency is 8 clock cycles.
14
Each pipeline converter stage converts its input voltage to a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX12557 functional diagram.
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
CLOCK
INAP T/H INAN
14-BIT PIPELINE ADC
DIGITAL ERROR CORRECTION
DATA FORMAT
OUTPUT DRIVERS
D0A TO D13A DORA
REFAP COMA REFAN
CHANNEL A REFERENCE SYSTEM
MAX12557
G/T
REFIN REFOUT SHREF REFBP COMB REFBN CHANNEL B REFERENCE SYSTEM
INTERNAL REFERENCE GENERATOR
DAV
OVDD
INBP T/H INBN
14-BIT PIPELINE ADC
DIGITAL ERROR CORRECTION CLOCK
DATA FORMAT
OUTPUT DRIVERS
D0B TO D13B DORB
DIFFCLK/SECLK CLOCK CLKP CLKN CLOCK DIVIDER DUTY-CYCLE EQUALIZER POWER CONTROL AND BIAS CIRCUITS
VDD
PD
DIV2 DIV4
GND
Figure 2. Functional Diagram
______________________________________________________________________________________
15
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Table 1. Reference Modes
BOND WIRE INDUCTANCE 1.5nH IN_P CPAR 2pF VDD *CSAMPLE 4.5pF VDD
VREFIN
MAX12557
REFERENCE MODE
BOND WIRE INDUCTANCE 1.5nH IN_N
Internal Reference Mode. REFIN is driven by REFOUT either through a 35% VREFOUT direct short or a resistive divider. to 100% VCOM_ = VDD / 2 VREFOUT VREF_P = VDD / 2 + 3/8 x VREFIN VREF_N = VDD / 2 - 3/8 x VREFIN Buffered External Reference Mode. An external 0.7V to 2.3V reference voltage is applied to REFIN. VCOM_ = VDD / 2 VREF_P = VDD / 2 + 3/8 x VREFIN VREF_N = VDD / 2 - 3/8 x VREFIN Unbuffered External Reference Mode. REF_P, REF_N, and COM_ are driven by external reference sources. The full-scale analog input range is (VREF_P - VREF_N) x 2/3.
CPAR 2pF
*CSAMPLE 4.5pF
0.7V to 2.3V
SAMPLING CLOCK *THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS: RIN =
1 fCLK x CSAMPLE
<0.5V
Figure 3. Internal T/H Circuit
Analog Inputs and Input Track-and-Hold (T/H) Amplifier
Figure 3 displays a simplified functional diagram of the input T/H circuit. This input T/H circuit allows for high analog input frequencies of 175MHz and beyond and supports a VDD / 2 common-mode input voltage. The MAX12557 sampling clock controls the switchedcapacitor input T/H architecture (Figure 3) allowing the analog input signals to be stored as charge on the sampling capacitors. These switches are closed (track mode) when the sampling clock is high and open (hold mode) when the sampling clock is low (Figure 4). The analog input signal source must be able to provide the dynamic currents necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these capacitors must be charged to one-half LSB accuracy within one-half of a clock cycle. The analog input of the MAX12557 supports differential or singleended input drive. For optimum performance with differential inputs, balance the input impedance of IN_P and IN_N and set the common-mode voltage to midsupply (VDD / 2). The MAX12557 provides the optimum common-mode voltage of VDD / 2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures 9, 10, and 11.
MAX12557. The power-down logic input (PD) enables and disables the reference circuit. REFOUT has approximately 17k to GND when the MAX12557 is powered down. The reference circuit requires 10ms to power up and settle to its final value when power is applied to the MAX12557 or when PD transitions from high to low. The internal bandgap reference produces a buffered reference voltage of 2.048V 1% at the REFOUT pin with a 50ppm/C temperature coefficient. Connect an external 0.1F bypass capacitor from REFOUT to GND for stability. REFOUT sources up to 1mA and sinks up to 0.1mA for external circuits with a 35mV/mA load regulation. Short-circuit protection limits IREFOUT to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to VDD. Similar to REFOUT, REFIN should be bypassed with a 4.7F capacitor to GND.
Reference Configurations
The MAX12557 full-scale analog input range is 2/3 x VREF with a VDD / 2 0.5V common-mode input range. VREF is the voltage difference between REFAP (REFBP) and REFAN (REFBN). The MAX12557 provides three modes of reference operation. The voltage at REFIN (VREFIN) selects the reference operation mode (Table 1). Connect REFOUT to REFIN either with a direct short or through a resistive divider to enter internal reference mode. COM_, REF_P, and REF_N are low-impedance outputs with VCOM_ = VDD / 2, VREFP = VDD / 2 + 3/8 x VREFIN, and VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P, REF_N, and COM_ each with a 0.1F capacitor
Reference Output
An internal bandgap reference is the basis for all the internal voltages and bias currents used in the
16
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC
to GND. Bypass REF_P to REF_N with a 10F capacitor. Bypass REFIN and REFOUT to GND with a 0.1F capacitor. The REFIN input impedance is very large (>50M). When driving REFIN through a resistive divider, use resistances 10k to avoid loading REFOUT. Buffered external reference mode is virtually identical to the internal reference mode except that the reference source is derived from an external reference and not the MAX12557's internal bandgap reference. In buffered external reference mode, apply a stable reference voltage source between 0.7V to 2.3V at REFIN. Pins COM_, REF_P, and REF_N are low-impedance outputs with VCOM_ = VDD / 2, VREF_P = VDD / 2 + 3/8 x VREFIN, and VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P, REF_N, and COM_ each with a 0.1F capacitor to GND. Bypass REF_P to REF_N with a 10F capacitor. Connect REFIN to GND to enter unbuffered external reference mode. Connecting REFIN to GND deactivates the on-chip reference buffers for COM_, REF_P, and REF_N. With their buffers deactivated, COM_, REF_P, and REF_N become high-impedance inputs and must be driven with separate, external reference sources. Drive VCOM_ to VDD / 2 5%, and drive REF_P and REF_N so VCOM_ = (VREF_P_ + VREF_N_) / 2. The analog input range is (V REF_P_ - V REF_N ) x 2/3. Bypass REF_P, REF_N, and COM_ each with a 0.1F capacitor to GND. Bypass REF_P to REF_N with a 10F capacitor. For all reference modes, bypass REFOUT with a 0.1F and REFIN with a 4.7F capacitor to GND. The MAX12557 also features a shared reference mode, in which the user can achieve better channel-to-channel matching. When sharing the reference (SHREF = VDD), externally connect REFAP and REFBP together to ensure that VREFAP = VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure that VREFAN = VREFBN. Connect SHREF to GND to disable the shared reference mode of the MAX12557. In this independent reference mode, a better channel-to-channel isolation is achieved. For detailed circuit suggestions and how to drive the ADC in buffered/unbuffered external reference mode, see the Applications Information section. The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the MAX12557 requires approximately 100 clock cycles to acquire and lock to new clock frequencies.
MAX12557
Clock Input and Clock Control Lines
The MAX12557 accepts both differential and singleended clock inputs with a wide 25% to 75% input clock duty cycle. For single-ended clock input operation, connect DIFFCLK/SECLK and CLKN to GND. Apply an external single-ended clock signal to CLKP. To reduce clock jitter, the external single-ended clock must have sharp falling edges. For differential clock input operation, connect DIFFCLK/SECLK to OV DD . Apply an external differential clock signal to CLKP and CLKN. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN enter high impedance when the MAX12557 is powered down (Figure 4). Low clock jitter is required for the specified SNR performance of the MAX12557. The analog inputs are sampled on the falling (rising) edge of CLKP (CLKN), requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 x log 2 x x fIN x t J where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For instance, assuming that clock jitter is the only noise source, to obtain the specified 72.5dB of SNR with an input frequency of 175MHz the system must have less than 0.21ps of clock jitter. However, in reality there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than 0.14ps to obtain the specified 72.5dBc of SNR at 175MHz. Clock-Divider Control Inputs (DIV2, DIV4) The MAX12557 features three different modes of sampling/clock operation (see Table 2). Pulling both control lines low, the clock-divider function is disabled and the converters sample at full clock speed. Pulling DIV4 low and DIV2 high enables the divide-by-two feature, which sets the sampling speed to one-half the selected clock frequency. In divide-by-four mode, the converter sampling speed is set to one-fourth the clock speed of the MAX12557. Divide-by-four mode is achieved by applying a high level to DIV4 and a low level to DIV2. The option to
17
Clock Duty-Cycle Equalizer
The MAX12557 has an internal clock duty-cycle equalizer, which makes the converter insensitive to the duty cycle of the signal applied to CLKP and CLKN. The converters allow clock duty-cycle variations from 25% to 75% without negatively impacting the dynamic performance.
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Table 2. Clock-Divider Control Inputs
VDD
DIV4
S1H
DIV2 0 1 0 1
FUNCTION Clock Divider Disabled fSAMPLE = fCLK Divide-by-Two Clock Divider fSAMPLE = fCLK / 2 Divide-by-Four Clock Divider fSAMPLE = fCLK / 4 Not Allowed
MAX12557
10k
0 0
CLKP 10k
1
S2H DUTY-CYCLE EQUALIZER 10k
1
S1L CLKN
cuitry can be latched with the rising edge of the conversion clock (CLKP - CLKN). Data-Valid Output DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. The MAX12557 output data changes on the falling edge of DAV, and DAV rises once the output data is valid. The falling edge of DAV is synchronized to have a 5.4ns delay from the falling edge of the input clock. Output data at D0A/B-D13A/B and DORA/B are valid from 7ns before the rising edge of DAV to 7ns after the rising edge of DAV. DAV enters high impedance when the MAX12557 is powered down (PD = OV DD ). DAV enters its highimpedance state 10ns after the rising edge of PD and becomes active again 10ns after PD transitions low. DAV is capable of sinking and sourcing 600A and has three times the driving capabilities of D0A/B-D13A/B and DORA/B. DAV is typically used to latch the MAX12557 output data into an external digital back-end circuit. Keep the capacitive load on DAV as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX12557, thereby degrading its dynamic performance. Buffering DAV
10k SWITCHES S1_ AND S2_ ARE OPEN DURING POWER-DOWN MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S2_ ARE OPEN IN SINGLE-ENDED CLOCK MODE.
S2L GND
Figure 4. Siimplified Clock Input Circuit
select either one-half or one-fourth of the clock speed for sampling provides design flexibility, relaxes clock requirements, and can minimize clock jitter.
System Timing Requirements
Figure 5 shows the timing relationship between the clock, analog inputs, DAV indicator, DOR_ indicators, and the resulting output data. The analog input is sampled on the falling (rising) edge of CLKP (CLKN) and the resulting data appears at the digital outputs 8 clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end cirDIFFERENTIAL ANALOG INPUT (IN_P-IN_N) (VREF_P - VREF_N) x 2/3 N+3 N-3 N-2 N-1 N N+1 N +2 N+4 N+5 N+6
N+7 N+8
N+9
(VREF_N - VREF_P) x 2/3 tAD CLKN CLKP tDAV DAV tSETUP D0_-D13_ tHOLD N-3 8.0 CLOCK-CYCLE DATA LATENCY DOR N-2 tCL tCH
N-1
N
N+1
N+2
N+3
N+4
N+5 tSETUP
N+6
N+7
N+8
N+9 tHOLD
Figure 5. System Timing Diagram 18 ______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC
externally isolates it from heavy capacitive loads. Refer to the MAX12557 EV kit schematic for recommendations of how to drive the DAV signal through an external buffer. Data Out-of-Range Indicator The DORA and DORB digital outputs indicate when the analog input voltage is out of range. When DOR_ is high, the analog input is out of range. When DOR_ is low, the analog input is within range. The valid differential input range is from (V REF_P - V REF_N ) x 2/3 to (V REF_N VREF_P) x 2/3. Signals outside of this valid differential range cause DOR_ to assert high as shown in Table 1. DOR is synchronized with DAV and transitions along with the output data D13-D0. There is an 8 clock-cycle latency in the DOR function as is with the output data (Figure 5). DOR_ is high impedance when the MAX12557 is in power-down (PD = high). DOR_ enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD's falling edge. Digital Output Data and Output Format Selection The MAX12557 provides two 14-bit, parallel, tri-state output buses. D0A/B-D13A/B and DORA/B update on the falling edge of DAV and are valid on the rising edge of DAV. The MAX12557 output data format is either Gray code or two's complement depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is set to two's complement. See Figure 8 for a binary-to-Gray and Gray-tobinary code conversion example. The following equations, Table 3, Figure 6, and Figure 7 define the relationship between the digital output and the analog input. Gray Code (G/T = 1): VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x (CODE10 - 8192) / 16,384 Two's Complement (G/T = 0): VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x CODE10 / 16,384 where CODE10 is the decimal equivalent of the digital output code as shown in Table 3.
MAX12557
Table 3. Output Codes vs. Input Voltage
GRAY-CODE OUTPUT CODE (G/T = 1) DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT OF OF DOR D13A-D0A D13A-D0A D13B-D0B D13B-D0B (CODE10) 1 0 0 0 0 0 0 0 0 0 1 0x2000 0x2000 0x2001 0x3003 0x3001 0x3000 0x1000 0x1001 0x0001 0x0000 0x0000 +16,383 +16,383 +16,382 +8194 +8193 +8192 +8191 +8190 +1 0 0 TWO'S-COMPLEMENT OUTPUT CODE (G/T = 0) DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT OF OF DOR D13A-D0A D13A-D0A D13B-D0B D13B-D0B (CODE10) 1 0 0 0 0 0 0 0 0 0 1 0x1FFF 0x1FFF 0x1FFE 0x0002 0x0001 0x0000 0x3FFF 0x3FFE 0x2001 0x2000 0x2000 +8191 +8191 +8190 +2 +1 0 -1 -2 -8191 -8192 -8192 VIN_P - VIN_N VREF_P = 2.418V VREF_N = 0.882V
BINARY D13A-D0A D13B-D0B
BINARY D13A-D0A D13B-D0B
10 0000 0000 0000 10 0000 0000 0000 10 0000 0000 0001 11 0000 0000 0011 11 0000 0000 0001 11 0000 0000 0000 01 0000 0000 0000 01 0000 0000 0001 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000
01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0010 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000
>+1.023875V (DATA OUT OF RANGE) +1.023875V +1.023750V +0.000250V +0.000125V +0.000000V -0.000125V -0.000250V -1.023875V -1.024000V <-1.024000V (DATA OUT OF RANGE)
______________________________________________________________________________________
19
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
1 LSB = 4/3 x (VREFP - VREFN) / 16,384 2/3 x (VREFP - VREFN) 0x1FFF 0x1FFE 0x1FFD GRAY OUTPUT CODE (LSB) 2/3 x (VREFP - VREFN) 0x2000 0x2001 0x2003 1 LSB = 4/3 x (VREFP - VREFN) / 16,384 2/3 x (VREFP - VREFN) 2/3 x (VREFP - VREFN)
TWO'S-COMPLEMENT OUTPUT CODE (LSB)
0x0001 0x0000 0x3FFF
0x3001 0x3000 0x1000
0x2003 0x2002 0x2001 0x2000 -8191 -8189 -1 0 +1 +8189 +8191
0x0002 0x0003 0x0001 0x0000 -8191 -8189 -1 0 +1 +8189 +8191
DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Two's-Complement Transfer Function (G/T = 0)
Figure 7. Gray-Code Transfer Function (G/T = 1)
The digital outputs D0A/B-D13A/B are high impedance when the MAX12557 is in power-down (PD = 1) mode. D0A/B-D13A/B enter this state 10ns after the rising edge of PD and become active again 10ns after PD transitions low. Keep the capacitive load on the MAX12557 digital outputs D0A/B-D13A/B as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX12557 and degrading its dynamic performance. Adding external digital buffers on the digital outputs helps isolate the MAX12557 from heavy capacitive loads. To improve the dynamic performance of the MAX12557, add 220 resistors in series with the digital outputs close to the MAX12557. Refer to the MAX12557 EV kit schematic for guidelines of how to drive the digital outputs through 220 series resistors and external digital output buffers.
In power-down mode all internal circuits are off, the analog supply current reduces to less than 50A, and the digital supply current reduces to 1A. The following list shows the state of the analog inputs and digital outputs in power-down mode. 1) INAP/B, INAN/B analog inputs are disconnected from the internal input amplifier (Figure 3). 2) REFOUT has approximately 17k to GND. 3) REFAP/B, COMA/B, REFAN/B enter a high-impedance state with respect to VDD and GND, but there is an internal 4k resistor between REFAP/B and COMA/B as well as an internal 4k resistor between REFAN/B and COMA/B. 4) D0A-D13A, D0B-D13B, DORA, and DORB enter a high-impedance state. 5) DAV enters a high-impedance state. 6) CLKP, CLKN clock inputs enter a high-impedance state (Figure 4). The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REF_P, REF_N, and COM_. In internal reference mode and buffered external reference mode the wake-up time is typically 10ms. When operating in the unbuffered external reference mode the wake-up time is dependent on the external reference drivers.
Power-Down Input
The MAX12557 has two power modes that are controlled with a power-down digital input (PD). With PD low, the MAX12557 is in its normal operating mode. With PD high, the MAX12557 is in power-down mode. The power-down mode allows the MAX12557 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX12557 parallel output bus goes high-impedance in power-down mode, allowing other devices on the bus to be accessed.
20
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
BINARY-TO-GRAY CODE CONVERSION 1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. D13 0 0 1 D11 1 0 1 1 D7 0 1 0 0 D3 1 1 0 D0 0 BIT POSITION BINARY GRAY CODE
GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT. D13 0 0 1 D11 01 1 0 D7 1 1 1 0 D3 1 0 1 D0 0 BIT POSITION GRAY CODE BINARY
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: GRAYX = BINARYX + BINARYX + 1 WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: GRAY12 = BINARY12 + BINARY13 GRAY12 = 1 + 0 GRAY12 = 1
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: BINARYX = BINARYX+1 + GRAYX WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: BINARY12 = BINARY13 + GRAY12 BINARY12 = 0 + 1 BINARY12 = 1
D13 0 0 + 1 1
D11 1 0 1 1
D7 0 1 0 0
D3 1 1 0
D0 0
BIT POSITION BINARY GRAY CODE
D13 0 + 0 1 1
D11 0 11 0
D7 1 1 1 0
D3 1 0 1
D0 0
BIT POSITION GRAY CODE BINARY
3) REPEAT STEP 2 UNTIL COMPLETE: GRAY11 = BINARY11 + BINARY12 GRAY11 = 1 + 1 GRAY11 = 0
3) REPEAT STEP 2 UNTIL COMPLETE: BINARY11 = BINARY12 + GRAY11 BINARY11 = 1 + 0 BINARY11 = 1 BIT POSITION BINARY GRAY CODE D13 0 0 1 + 1 0 1 D11 1 1 0 D7 1 1 1 0 D3 1 0 1 D0 0 BIT POSITION GRAY CODE BINARY
D13 0 0 1 1 + 1 0
D11 01 1
D7 0 1 0 0
D3 1 1 0
D0 0
4) THE FINAL GRAY-CODE CONVERSION IS: D13 0 0 1 1 D11 1 0 0 1 1 1 1 0 D7 0 1 1 1 0 1 0 0 D3 1 1 1 0 0 1 D0 0 0 BIT POSITION BINARY GRAY CODE
4) THE FINAL BINARY CONVERSION IS: D13 0 0 1 1 D11 0 1 1 0 1 1 0 1 D7 1 0 1 1 1 0 0 0 D3 1 1 0 1 1 0 D0 0 0 BIT POSITION GRAY CODE BINARY
EXCLUSIVE OR TRUTH TABLE FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT FORMAT OF THE MAX12557 IS TWO'S-COMPLEMENT BINARY, HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE MUST BE INSERTED TO REFLECT TRUE OFFSET BINARY FORMAT. A 0 0 1 1 B 0 1 0 1 Y = A + 0 1 1 0 B
Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion ______________________________________________________________________________________ 21
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Applications Information
Using Transformer Coupling
In general, the MAX12557 provides better SFDR and THD with fully differential input signals than singleended input drive, especially for input frequencies above 125MHz. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode. An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12557 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 9 is good for frequencies up to Nyquist (fCLK / 2). The circuit of Figure 10 converts a single-ended input signal to fully differential just as Figure 9. However, Figure 10 utilizes an additional transformer to improve the common-mode rejection allowing high-frequency signals beyond the Nyquist frequency. A set of 75 and 113 termination resistors provide an equivalent 50 termination to the signal source. The second set of termination resistors connects to COM_ providing the correct input common-mode voltage. Two 0 resistors in series with the analog inputs allow high IF input frequencies. These 0 resistors can be replaced with lowvalue resistors to limit the input bandwidth.
Single-Ended AC-Coupled Input Signal
Figure 11 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.
24.9 IN_P 5.6pF 0.1F VIN N.C.
VIN 0.1F
MAX4108
1 T1 5 3
6 2 0.1F 4
MAX12557
COM_
100
0 IN_P 5.6pF 24.9
MAX12557
COM_ 0.1F
MINICIRCUITS TT1-6 OR T1-1T
100
24.9 IN_N 5.6pF
24.9 IN_N 5.6pF
Figure 9. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist
Figure 11. Single-Ended, AC-Coupled Input Drive
0* 0.1F VIN N.C. 1 5 T1 6 2 75 1% N.C. 75 1% N.C. 1 5 T2 6 2 113 0.5% N.C. 0.1F 3 4 MINICIRCUITS ADT1-1WT 3 4 MINICIRCUITS ADT1-1WT 113 0.5% 0* IN_N 5.6pF *0 RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH. COM_ IN_P 5.6pF
MAX12557
Figure 10. Transformer-Coupled Input Drive for Input Frequencies beyond Nyquist
22
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
3.3V
0.1F
2.2F
VDD REFIN 0.1F 1 5 16.2k 1F 3 5 1
MAX4230
REF_P 0.1F
0.1F
2.048V
MAX12557
47 300F 6V REF_N
10F
0.1F
MAX6029 (EUK21)
2
4
2 REFOUT 0.1F GND COM_
0.1F
1.47k
0.1F
NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING UP TO 15mA AND SINKING UP TO 30mA OF OUTPUT CURRENT.
3.3V
0.1F
2.2F
VDD REFIN REF_P 0.1F
MAX12557
REF_N
10F
0.1F
0.1F
REFOUT 0.1F GND
COM_ 0.1F
Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference
Buffered External Reference Drives Multiple ADCs
The buffered external reference mode allows for more control over the MAX12557 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50M. Figure 12 shows the MAX6029 precision 2.048V bandgap reference used as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through a single-pole 10Hz LP filter to the MAX4230.
The MAX4250 buffers the 2.048V reference and provides additional 10Hz LP filtering before its output is applied to the REFIN input of the MAX12557.
Unbuffered External Reference Drives Multiple ADCs
The unbuffered external reference mode allows for precise control over the MAX12557 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal refer23
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
3.3V
3V 0.1F 1 5 20k 1% 0.1F 20k 1% 1 4
MAX4230
0.1F
2.2F
MAX6029 (EUK30)
2
REF_P
VDD REFOUT
10F 2.413V 47 0.1F 330F 6V 1.47k
0.1F
0.1F
MAX12557
REF_N
0.47F 52.3k 1%
3
10F 6V
COM_ 0.1F 1 4
MAX4230
GND
REFIN
1.647V 47 3.3V 10F 6V 1.47k 0.1F 2.2F 330F 6V
3 52.3k 1%
1 4 20k 1%
MAX4230
0.880V 47 0.1F 10F 6V 1.47k 0.1F 330F 6V 10F 0.1F REF_P VDD REFOUT 0.1F
3
20k 1%
MAX12557
REF_N
20k 1% COM_ 0.1F REFIN
GND
Figure 13. External Unbuffered Reference Driving Multiple ADCs
ence, allowing REF_P, REF_N, and COM_ to be driven directly by a set of external reference sources. Figure 13 uses a MAX6029 precision 3.000V bandgap reference as a common reference for multiple converters. A seven-component resistive divider chain follows the MAX6029 voltage reference. The 0.47F capacitor along this chain creates a 10Hz LP filter. Three MAX4230 amplifiers buffer taps along this resistor chain providing 2.413V, 1.647V, and 0.880V to the MAX12557 REF_P, REF_N, and COM_ reference inputs. The feedback around the MAX4230 op amps provides additional 10Hz LP filtering. Reference voltages 2.413V and 0.880V set the full-scale analog input
24
range for the converter to 1.022V ([VREF_P - VREF_N] x 2/3). Note that one single power supply for all active circuit components removes any concern regarding powersupply sequencing when powering up or down.
Grounding, Bypassing, and Board Layout
The MAX12557 requires high-speed board layout design techniques. Refer to the MAX12557 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC
mount devices for minimum inductance. Bypass VDD to GND with a 220F ceramic capacitor in parallel with at least one 10F, one 4.7F, and one 0.1F ceramic capacitor. Bypass OVDD to GND with a 220F ceramic capacitor in parallel with at least one 10F, one 4.7F, and one 0.1F ceramic capacitor. High-frequency bypassing/decoupling capacitors should be located as close as possible to the converter supply pins. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All grounds and the exposed backside paddle of the MAX12557 must be connected to the same ground plane. The MAX12557 relies on the exposed backside paddle connection for a low-inductance ground connection. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90 turns. Ensure that the differential, analog input network layout is symmetric and that all parasitic components are balanced equally. Refer to the MAX12557 EV kit data sheet for an example of symmetric input layout.
Gain Error
Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive fullscale MAX12557 transition occurs at 1.5 LSBs below positive full scale, and the negative full-scale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points.
MAX12557
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with a -35dBFS amplitude. This parameter captures the thermal and quantization noise characteristics of the data converter and can be used to help calculate the overall noise figure of a digital receiver signal path.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR[max] = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2 through HD7), and the DC offset. SNR = 20 x log (SIGNALRMS / NOISERMS)
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer function from a straight line. For the MAX12557, this straight line is between the endpoints of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX12557, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.
Offset Error
Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally the midscale MAX12557 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.
______________________________________________________________________________________
25
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as:
V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 x log V1
CLKN CLKP tAD ANALOG INPUT tAJ SAMPLED DATA
where V1 is the fundamental amplitude, and V2 through V7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2 through HD7).
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
T/H
HOLD
TRACK
HOLD
Figure 14. T/H Aperture Timing
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 14).
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones fIN1 and fIN2. The individual input tone levels are at -7dBFS. The intermodulation products are as follows: 2nd-Order Intermodulation Products (IM2): fIN1 + fIN2, fIN2 - fIN1 3rd-Order Intermodulation Products (IM3): 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 4th-Order Intermodulation Products (IM4): 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1, 2 x fIN1 - 2 x fIN2, 2 x fIN1 + 2 x fIN2, 2 x fIN2 - 2 x fIN1 5th-Order Intermodulation Products (IM5): 3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x fIN2, 3 x fIN2 + 2 x fIN1, 4 x fIN1 - fIN2, 4 x fIN2 - fIN1, 4 x fIN1 + fIN2, 4 x fIN2 + fIN1
Full-Power Bandwidth
A large -0.2dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as the full-power input bandwidth frequency.
Output Noise (nOUT)
The output noise (nOUT) parameter is similar to thermal plus quantization noise and is an indication of the converter's overall noise performance. No fundamental input tone is used to test for nOUT. IN_P, IN_N, and COM_ are connected together and 1024k data points are collected. nOUT is computed by taking the RMS value of the collected data points after the mean is removed.
Overdrive Recovery Time
Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX12557 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by 10%. The MAX12557 requires one clock cycle to recover from the overdrive condition.
3rd-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones fIN1 and fIN2. The individual input tone levels are at -7dBFS. The 3rdorder intermodulation products are 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1.
Crosstalk
Coupling onto one channel being driven by a (-0.5dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components.
Aperture Jitter
Figure 14 shows the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
26
______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC
Gain Matching
Gain matching is a figure of merit that indicates how well the gains between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in gain is reported (typically in dB) as gain matching.
REFOUT SHREF REFIN
Pin Configuration
DORA
MAX12557
TOP VIEW
OVDD
D13A
D12A
D11A
D10A
D9A
D8A
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52 51 D6A 50 D5A 49 D4A 48 D3A 47 D2A 46 D1A 45 D0A 44 DAV
GND
1 2 3 4 5 6 7 8 9
Offset Matching
Like gain matching, offset matching is a figure of merit that indicates how well the offsets between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in offset is reported (typically in %FSR) as offset matching.
INAP INAN GND GND COMA REFAP REFAN GND
D7A
43 OVDD 42 DORB 41 D13B 40 D12B 39 D11B 38 D10B 37 D9B 36 D8B 35 D7B
VDD
VDD
REFBN 10 REFBP 11 COMB 12 GND 13 GND 14 INBN 15 INBP 16 GND 17
MAX12557
EXPOSED PADDLE (GND)
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
CLKN
DIFFCLK/SECLK
CLKP
DIV4
VDD
G/T
PD
D0B
D1B
D2B
D3B
D4B
D5B
DIV2
THIN QFN
______________________________________________________________________________________
OVDD
D6B
VDD
VDD
VDD
VDD
27
Dual, 65Msps, 14-Bit, IF/Baseband ADC MAX12557
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
68L QFN THIN.EPS
PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm
21-0142
C
1
2
PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm
21-0142
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
This datasheet has been downloaded from: www..com Datasheets for electronic components.

▲Up To Search▲

Price & Availability of MAX12557

	To Download MAX12557 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .